PIC16F72 Data Sheet. 28-Pin, 8-Bit CMOS FLASH Microcontroller with A/D Converter Microchip Technology Inc. DS39597B

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M PIC16F72 Data Sheet 28-Pin, 8-Bit CMOS FLASH Microcontroller with A/D Converter 2002 Microchip Technology Inc. DS357B Note the following details of the code protection feature on PICmicro MCUs. The PICmicro
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M PIC16F72 Data Sheet 28-Pin, 8-Bit CMOS FLASH Microcontroller with A/D Converter 2002 Microchip Technology Inc. DS357B Note the following details of the code protection feature on PICmicro MCUs. The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microid, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dspic, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, microport, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfpic, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1 and Mountain View, California in March The Company s quality system processes and procedures are QS-000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 001 certified. DS357B - page ii 2002 Microchip Technology Inc. M PIC16F72 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter Device Included: PIC16F72 High Performance RISC CPU: Only 35 single word instructions to learn All single cycle instructions except for program branches, which are two-cycle Operating speed: DC - 20 MHz clock input DC ns instruction cycle 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) Pinout compatible to PIC16C72/72A and PIC16F872 Interrupt capability Eight-level deep hardware stack Direct, Indirect and Relative Addressing modes Peripheral Features: High Sink/Source Current: 25 ma Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Capture, Compare, PWM (CCP) module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit 8-bit, 5-channel analog-to-digital converter Synchronous Serial Port (SSP) with SPI (Master/Slave) and I 2 C (Slave) Brown-out detection circuitry for Brown-out Reset (BOR) CMOS Technology: Low power, high speed CMOS FLASH technology Fully static design Wide operating voltage range: 2.0V to 5.5V Industrial temperature range Low power consumption: - 0.6 ma 3V, 4 MHz - 20 µa 3V, 32 khz - 1 µa typical standby current Pin Diagrams PDIP, SOIC, SSOP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL QFN PIC16F RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKI OSC2/CLKO PIC16F RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 21 RB3 Special Microcontroller Features: RB7/PGD RB6/PGC RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA RB2 RB1 RB0/INT VDD VSS RC7 1,000 erase/write cycle FLASH program memory typical Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options In-Circuit Serial Programming (ICSP ) via 2 pins Processor read access to program memory 2002 Microchip Technology Inc. DS357B-page 1 Key Reference Manual Features PIC16F72 Operating Frequency DC - 20 MHz RESETS and (Delays) POR, BOR, (PWRT, OST) FLASH Program Memory - (14-bit words, 1000 E/W cycles) 2K Data Memory - RAM (8-bit bytes) 128 Interrupts 8 I/O Ports PORTA, PORTB, PORTC Timers Timer0, Timer1, Timer2 Capture/Compare/PWM Modules 1 Serial Communications SSP 8-bit A/D Converter 5 channels Instruction Set (No. of Instructions) 35 DS357B-page Microchip Technology Inc. Table of Contents 1.0 Device Overview Memory Organization I/O Ports Reading Program Memory Timer0 Module Timer1 Module Timer2 Module Capture/Compare/PWM (CCP) Module Synchronous Serial Port (SSP) Module Analog-to-Digital Converter (A/D) Module Special Features of the CPU Instruction Set Summary Development Support Electrical Characteristics DC and AC Characteristics Graphs and Tables Package Marking Information Appendix A: Revision History Appendix B: Conversion Considerations Index On-Line Support Reader Response Product Identification System TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via at or fax the Reader Response Form in the back of this data sheet to (480) We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: Microchip s Worldwide Web site; Your local Microchip sales office (see last page) The Microchip Corporate Literature Center; U.S. FAX: (480) When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at to receive the most current information on all of our products Microchip Technology Inc. DS357B-page 3 NOTES: DS357B-page Microchip Technology Inc. 1.0 DEVICE OVERVIEW This document contains device specific information for the operation of the PIC16F72 device. Additional information may be found in the PICmicro Mid-Range MCU Reference Manual (DS33023), which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F72 belongs to the Mid-Range family of the PICmicro devices. A block diagram of the device is shown in Figure 1-1. The program memory contains 2K words, which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes. There are 22 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: External interrupt Change on PORTB interrupt Timer0 clock input Timer1 clock/oscillator Capture/Compare/PWM A/D converter SPI/I 2 C Table 1-1 details the pinout of the device with descriptions and details for each pin. FIGURE 1-1: PIC16F72 BLOCK DIAGRAM Program Bus OSC1/CLKI OSC2/CLKO FLASH Program Memory 2K x Instruction reg Instruction Decode & Control Timing Generation 8 13 Program Counter 8-Level Stack (13-bit) Direct Addr 7 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Data Bus RAM File Registers 128 x 8 RAM Addr (1) 8 3 Addr MUX ALU W reg 8 FSR reg 8 Indirect Addr STATUS reg MUX PORTA PORTB PORTC RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 MCLR VDD, VSS Timer0 Timer1 Timer2 A/D Synchronous Serial Port CCP1 Note 1: Higher order bits are from the STATUS register Microchip Technology Inc. DS357B-page 5 TABLE 1-1: Pin Name PIC16F72 PINOUT DESCRIPTION PDIP, SOIC, SSOP Pin# MLF Pin# I/O/P Type Buffer Type Description OSC1/CLKI 6 I ST/CMOS (3) Oscillator crystal input/external clock source input. OSC2/CLKO 10 7 O Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 26 I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN I/O TTL RA0 can also be analog input0. RA1/AN I/O TTL RA1 can also be analog input1. RA2/AN2 4 1 I/O TTL RA2 can also be analog input2. RA3/AN3/VREF 5 2 I/O TTL RA3 can also be analog input3 or analog reference voltage. RA4/T0CKI 6 3 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/AN4/SS 7 4 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT I/O TTL/ST (1) RB0 can also be the external interrupt pin. RB I/O TTL RB I/O TTL RB I/O TTL RB I/O TTL Interrupt-on-change pin. RB I/O TTL Interrupt-on-change pin. RB6/PGC I/O TTL/ST (2) Interrupt-on-change pin. Serial programming clock. RB7/PGD I/O TTL/ST (2) Interrupt-on-change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/ 11 8 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. T1CKI RC1/T1OSI 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP I/O ST RC2 can also be the Capture1 input/compare1 output/ PWM1 output. RC3/SCK/SCL I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I 2 C modes. RC4/SDI/SDA I/O ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I 2 C mode). RC5/SDO I/O ST RC5 can also be the SPI Data Out (SPI mode). RC I/O ST RC I/O ST VSS 8, 1 5, 16 P Ground reference for logic and I/O pins. VDD P Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS357B-page Microchip Technology Inc. 2.0 MEMORY ORGANIZATION There are two memory blocks in the PIC16F72 device. These are the program memory and the data memory. Each block has separate buses so that concurrent access can occur. Program memory and data memory are explained in this section. Program memory can be read internally by the user code (see Section 4.0). The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the core are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). 2.1 Program Memory Organization PIC16F72 devices have a 13-bit program counter capable of addressing a 8K x 14 program memory space. The address range for this program memory is 0000h - 07FFh. Accessing a location above the physically implemented address will cause a wraparound. The RESET Vector is at 0000h and the Interrupt Vector is at 0004h. FIGURE 2-1: PROGRAM MEMORY MAP AND STACK 2.2 Data Memory Organization The Data Memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS 6 ) and RP0 (STATUS 5 ) are the bank select bits. RP1:RP0 Bank Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain SFRs. Some high use SFRs from one bank may be mirrored in another bank, for code reduction and quicker access (e.g., the STATUS register is in Banks 0-3) GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly, through the File Select Register FSR (see Section 2.5). CALL, RETURN RETFIE, RETLW PC 12:0 13 Stack Level 1 Stack Level 8 RESET Vector 0000h User Memory Space Interrupt Vector On-chip Program Memory 0004h 0005h 07FFh 0800h 1FFFh 2002 Microchip Technology Inc. DS357B-page 7 FIGURE 2-2: PIC16F72 REGISTER FILE MAP File Address File Address File Address File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES ADCON0 General Purpose Register 6 Bytes 00h 01h 02h 03h 04h 05h 06h 07h 08h 0h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 1h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIE1 PCON PR2 SSPADD SSPSTAT 80h 81h 82h 83h 84h 85h 86h 87h 88h 8h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 0h 1h 2h 3h 4h 5h 6h 7h 8h h Ah Bh Ch Dh Eh Fh ADCON1 General A0h Purpose Register 32 Bytes BFh C0h accesses 40h-7Fh Indirect addr.(*) TMR0 PCL STATUS FSR PORTB PCLATH INTCON PMDATL PMADRL PMDATH PMADRH accesses 20h-7Fh 100h 101h 102h 103h 104h 105h 106h 107h 108h 10h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 11Fh 120h Indirect addr.(*) OPTION PCL STATUS FSR TRISB PCLATH INTCON PMCON1 accesses A0h -BFh accesses 40h -7Fh 180h 181h 182h 183h 184h 185h 186h 187h 188h 18h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 10h 1Fh 1A0h 1BFh 1C0h 7Fh Bank 0 Bank 1 FFh 17Fh Bank 2 Bank 3 1FFh Unimplemented data memory locations, read as 0. * Not a physical register. DS357B-page Microchip Technology Inc. 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Bank 0 00h (1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) h TMR0 Timer0 Module s Register xxxx xxxx 2,13 02h (1) PCL Program Counter's (PC) Least Significant Byte h (1) STATUS IRP RP1 RP0 TO PD Z DC C xxx 12 04h (1) FSR Indirect Data Memory Address Pointer xxxx xxxx 1 05h PORTA PORTA Data Latch when written: PORTA pins when read --0x h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 23 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 25 08h Unimplemented 0h Unimplemented 0Ah (1,2) PCLATH Write Buffer for the upper 5 bits of the Program Counter Bh (1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF x 14 0Ch PIR1 ADIF SSPIF CCP1IF TMR2IF TMR1IF Dh Unimplemented 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 31 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 31 10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON h TMR2 Timer2 Module s Register h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 43,48 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 38,3,41 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 38,3,41 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M h-1Dh Unimplemented 1Eh ADRES A/D Result Register xxxx xxxx 53 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved. Shaded locations are unimplemented, read as 0. Note 1: These registers can be addressed from any bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC 12:8 whose contents are transferred to the upper byte of the program counter. 3: This bit always reads as a Microchip Technology Inc. DS357B-page TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Bank 1 80h (1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS h (1) PCL Program Counter s (PC) Least Significant Byte h (1) STATUS IRP RP1 RP0 TO PD Z DC C xxx 12 84h (1) FSR Indirect Data Memory Address Pointer xxxx xxxx 1 85h TRISA PORTA Data Direction Register h TRISB PORTB Data Direction Register h TRISC PORTC Data Direction Register h Unimplemented 8h Unimplemented 8Ah (1,2) PCLATH Write Buffer for th
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