MATrix-II. VLSI Protoboard. User s Manual Rev : 3

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MATrix-II VLSI Protoboard User s Manual Rev : 3 ni logic Pvt. Ltd. (ni2designs) 201/202, C-2, Saudamani Commercial Complex, Bhusari Colony, Paud Road, Kothrud, Pune Telefax : /8
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MATrix-II VLSI Protoboard User s Manual Rev : 3 ni logic Pvt. Ltd. (ni2designs) 201/202, C-2, Saudamani Commercial Complex, Bhusari Colony, Paud Road, Kothrud, Pune Telefax : /8 Preface: This manual is for the users of MATrix-II with in-depth details of product including reference designs and examples. Copyrights: We acknowledge that the following organizations claim trademark rights in their respective products or services mentioned in this document, specifically: Altera, Quartus-II, ACEX, ByteBlaster, etc Xilinx, ISE, impact, Spartan-II, etc. For further details and queries contact: ni logic Pvt. Ltd. (ni2designs) 201/202, C-2, Saudamani Commercial Complex, Bhusari Colony, Paud Road, Kothrud, Pune Telefax : /8 ni logic Pvt. Ltd., Pune 2 Table of Contents MATrix-II VLSI Protoboard User Manual Rev : 3 1. Introduction a. Introduction to Programmable logic and PLDs b. Product Introduction 2. Features and Specifications 3. Getting Started 4. Diagrams a. I/O Connections for Xilinx FPGA b. I/O Connections for Altera FPGA c. I/O Connections for CPLDs d. Baseboard legend diagram 5. Precautions 6. Design Flow a. PLD design flow b. Microcontroller design flow c. Xilinx webpack design flow d. Altera Quartus-II design flow e. Keil design flow 7. Configuration/Downloading a. Types of Modes b. Jumper setting for mode selection c. Using Variable frequency generator d. Programming Atmel Microcontroller 8. Pin Assignments 9. Jumper settings 10. Using External Adaptors 11. How to use Pico-blaze 12. Sample codes 13. Glossary 14. Global Design Hints 15. Troubleshooting 16. Device Features ni logic Pvt. Ltd., Pune 3 Chapter 1: Introduction 1.a What is Programmable Logic? In the world of digital electronic systems, there are three basic kinds of devices: memory, microprocessors, and logic. Memory devices store random information such as the contents of a spreadsheet or database. Microprocessors execute software instructions to perform a wide variety of tasks such as running a word processing program or video game. Logic devices provide specific functions, including device-to-device interfacing, data communication, signal processing, data display, timing and control operations, and almost every other function a system must perform. Fixed Logic versus Programmable Logic Logic devices can be classified into two broad categories - fixed and programmable. As the name suggests, the circuits in a fixed logic device are permanent, they perform one function or set of functions - once manufactured, they cannot be changed. On the other hand, programmable logic devices (PLDs) are standard, off-the-shelf parts that offer customers a wide range of logic capacity, features, speed, and voltage characteristics - and these devices can be changed at any time to perform any number of functions. With fixed logic devices, the time required to go from design, to prototypes, to a final manufacturing run can take from several months to more than a year, depending on the complexity of the device. And, if the device does not work properly, or if the requirements change, a new design must be developed. The up-front work of designing and verifying fixed logic devices involves substantial non-recurring engineering costs, or NRE. These NRE costs can run from a few hundred thousand to several million dollars. With programmable logic devices, designers use inexpensive software tools to quickly develop, simulate, and test their designs. Then, a design can be quickly programmed into a device, and immediately tested in a live circuit. There are no NRE costs and the final design is completed much faster than that of a custom, fixed logic device. Another key benefit of using PLDs is that during the design phase customers can change the circuitry as often as they want until the design operates to their satisfaction. That's because PLDs are based on re-writable memory technology - to change the design, the device is simply reprogrammed. Once the design is final, customers can go into immediate production by simply programming as many PLDs as they need with the final software design file. CPLDs and FPGAs The two major types of programmable logic devices are field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Of the two, FPGAs offer the highest amount of logic density, the most features, and the highest performance. The largest FPGA provides millions of system gates (the relative density of logic). These advanced devices also offer features such as built-in hardwired IP cores (such as the IBM Power PC, PCI cores, microcontrollers, peripherals, etc), substantial amounts of memory, clock management systems, and support for many of the latest, very fast device-to-device signaling technologies. FPGAs are used in a wide variety of applications ranging from data processing and storage, to instrumentation, telecommunications, and digital signal processing. CPLDs, by contrast, offer much smaller amounts of logic - up to about 10,000 gates. But CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications. Low power CPLDs are also available and are very inexpensive, making them ideal for cost-sensitive, battery-operated, portable applications such as mobile phones and digital handheld assistants. The PLD Advantage Fixed logic devices and PLDs both have their advantages. Fixed logic devices, for example, are often more appropriate for large volume applications because they can be mass-produced more economically. For certain applications where the very highest performance is required, fixed logic devices may also be the best choice. ni logic Pvt. Ltd., Pune 4 However, programmable logic devices offer a number of important advantages over fixed logic devices, including: PLDs offer customers much more flexibility during the design cycle because design iterations are simply a matter of changing the programming file, and the results of design changes can be seen immediately in working parts. PLDs do not require long lead times for prototypes or production parts - the PLDs are already on a distributor's shelf and ready for shipment. PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets - PLD suppliers incur those costs when they design their programmable devices and are able to amortize those costs over the multi-year lifespan of a given line of PLDs. PLDs can be reprogrammed even after a piece of equipment is shipped to a customer. In fact, thanks to programmable logic devices, a number of equipment manufacturers now have the ability to add new features or upgrade products that already are in the field. To do this, they simply upload a new programming file to the PLD, via the Internet, creating new hardware logic in the system. Conclusion The value of programmable logic has always been its ability to shorten development cycles for electronic equipment manufacturers and help them get their product to market faster. As PLD suppliers continue to integrate more functions inside their devices, reduce costs, and increase the availability of time-saving IP cores, programmable logic is certain to expand its popularity with digital designers. 1.b Product Information The MATrix-II ( Multiple Application Tricks) is a low cost universal platform for testing and verifying designs based on the Xilinx and Altera PLDs. The purpose of MATrix-II is to teach the basic concepts of VLSI designing along with various electronics circuits. The MATrix-II has been revised and also extended to some basic electronic circuits for application development and their realization. Using this protoboard the user can verify his PLD designs with complete applications and also it gives a complete set of modules for project development for final year students. MATrix-II supports multiple vendor devices from Xilinx and Altera, who are world leader in PLD manufacturing. The MATrix-II supports Spartan-2 and XC9500 series of devices from Xilinx; and ACEX 1K and MAX7000s series of devices from Altera. The basic version of MATrix-II comes with 50,000 gate XC2S50-PQ208 FPGA, XC9572 or MAX7128S CPLD and EP1k50TQ144 FPGA from Altera along with supporting circuitry to ease prototype efforts (optional PLD modules available). MATrix-II comes along with various adaptors, which are optional to user. Every adaptor is pluggable with baseboard with the help of connectors. 1. Keypad adaptor 2. LCD adaptor 3. Dot matrix rolling display card 4. Relay card 5. 89C51 adaptor 6. ADC/DAC adaptor With these adaptors user expands his choice and features to prototype and solve his design needs and requirements. Above modules are optional to the baseboard and can be used by plugging into it. ni logic Pvt. Ltd., Pune 5 Chapter 2: Features & Specifications 2.a Features and Specifications Multi-vendor device support for Xilinx and Altera PLDs. Packages supported PLCC84, TQ144 and PQ208. Upto 140 user I/Os. Voltage support to +1.2V, +2.5V, +3.3V & +5V devices, All FPGA I/Os accessible through headers. Four Multiplexed 7-Segment displays (with segment map). Interface to RS232 with 9-pin D-type connector. User selectable configuration modes, using FLASH PROM / JTAG / Slave Serial. Byte-blaster cable interface for configuration of Altera FPGAs. On board 8-MHz Clock oscillator (user selectable). Variable frequency generator (from 100 Hz to 10 KHz range). Higher frequency board support. Configurable 24 switches as I/P or O/P. 16 digital LED indicated outputs. Power on Reset and configuration reset key. Support for different I/O Standards. 4x4 Keyboard matrix card. Interface to Atmel AT89s8252 microcontroller. Facility for I 2 C interface. 8-bit ADC/DAC add-on card. Four 5x7 Dot Matrix displays. Optically isolated relay card. 16x2 character LCD display with contrast control. Short circuit protection circuit. ni logic Pvt. Ltd., Pune 6 2.b Individual Module Specification * Keyboard adaptor o 4x4 membrane keypad Liquid Crystal Display (LCD) adapter o 16 x 2 characters LCD display with Contrast control Relay Card o 2 Optically isolated relays o NC, NO, COMM I/Os on power header o Relay ON indication Dot Matrix rolling display panel o Matrix of four 5x7 LED display o Total 140 LED matrix on board. Pluggable Micro controller Card o Atmel AT89S8252 ISP microcontroller o 8KB ISP Flash & 2KB of EEPROM. o Coupled with FPGA for embedded application development. o All 32 I/O lines accessible to FPGA. o On board reset circuit o Timer, interrupt and ISP ports. ADC/DAC Card o 8 channel ADC 0809 with sampling speed of 20KHz on single channel. o Single channel DAC0800 with 150ns settling time. o Facility for onboard gain and reference voltage adjustment. Xilinx CPLD Module o XC9572 PC84-15C containing 72 macrocells with 1,600 usable gates. Xilinx FPGA Module o 50,000 gate density XC2S50 PQ208-5 FPGA from Xilinx. Altera CPLD Module o EPM7128SLC84-15C device containing 128 macrocells with 2,500 usable gates. Altera FPGA Module o 50,000 gate density EP1K50 TQ144-3C FPGA from Altera. *Note: Above module are optional with the product. ni logic Pvt. Ltd., Pune 7 Power supply Required voltages are generated onboard through regulators; other supply voltages are applied from external power supply. Here is the list of voltages on board used. +12V +5V -5V +3.3V +2.5V +1.2V * Note: The above specifications and features of product are subject to change with new versions of product. Connectors Header Name Ident Relay Header JP5 Digital I/Os and Rolling display JP Header JP2 LCD Header JP4 ADC/DAC & Keypad JP1 PLD Header JH1, JH2, JH3, JH4 Power supply JP6 Jumpers Jumpers are provided on baseboard for selection of 1. Configuration mode pins 2. Bypassing the PROM 3. Selecting configurable Input or Output 4. Selecting the O/P LEDs. o J8-J11 Mode selection headers o J6, J7 PROM bypass o S0-S7 SW1 o S8-S15 SW2 o S16-S23 SW3 Downloading cable For Xilinx PLDs For configuration of Xilinx FPGA and CPLD from PC, a 9 pins D Type connector is provided on baseboard. The MATrix can be connected to PC's parallel port with cable provided having 25 pins D Type connector on other end. For Altera PLDs Altera PLD adaptors have onboard JTAG header. User has to connect the programming JTAG cable provided on this header and other end to PCs parallel port to configure the PLDs. *Note: Kindly remove the cables by its headers only. Removing the cables by handling its wire may cause damage to its joints. ni logic Pvt. Ltd., Pune 8 Chapter 3: Getting Started After going through this chapter user will be able to start using board with ease. A user has to see this chapter as introduction to steps involved in using the board, its handling and programming of the devices. Step 1:. Connect the power cable to the Universal board as shown in figure. Applying Power to the Board To power-up the Universal board place switch in the ON position. When power is supplied to the Universal board, LED D1 turns on, indicating the board has power. Step 2:- Connect the programming cable on programming port as shown in figure.. Programming Port Connect the JTAG cable DB 9 pin male plug to DB 9 pin Female connector on programming port P2 and connect the other end to the parallel port on your PC This allows you to directly configure the Xillinx PLD. ni logic Pvt. Ltd., Pune 9 Step 3:- Plug the Xilinx FPGA (XC2S50 PQ208) card on base board (white dot should be match both PLD card and baseboard). Step 4:- Make the jumper settings for programming mode as shown in figure below (short 2-3). These jumper block settings control the FPGA s configuration mode or PROM Configuration mode. As per the settings below, the Xilinx FPGA or CPLD would be programmed in Boundary scan or JTAG mode. ni logic Pvt. Ltd., Pune 10 Step 5:- Set the programming mode to JTAG by setting the mode selection switch into position shown as below. This switch (SW6) is used to put the FPGA in the different programming mode. It is recommended to use JTAG mode for programming from PC. At this point your board is ready to accept programming file from Xilinx impact programmer from desktop PC. Now refer chapter Using EDA Tools, page no. 19 to follow the implementation steps of the Xilinx ISE software. There after generating the programming file from it, program the device on board and check your functionality. ni logic Pvt. Ltd., Pune 11 Chapter 4: Diagrams 8051 Header LCD Header ADC/DAC Keypad Header Dot Matrix Display and I/Os Relay Header 7 Seg. Displays Spartan-II FPGA PQ208 Config. Reset Functional Reset Clock Osc. (8 MHz) Var. Clock (in KHz) RS O/P LEDs Jumpers 24 configurable switches 4.a System Connection Diagram (Xilinx FPGA) ni logic Pvt. Ltd., Pune 12 ADC/DAC Keypad Header Dot Matrix Display and I/Os Relay Header 7 Seg. Displays ACEX1K FPGA TQ144 Functional Reset Clock Osc. (8 MHz) Var. Clock (in KHz) RS O/P LEDs Jumpers 24 configurable switches 4.b System Connection Diagram (Altera FPGA) ni logic Pvt. Ltd., Pune 13 Keypad Header Relay Header 7 Seg. Displays CPLD PLCC84 Functional Reset Clock Osc. (8 MHz) Var. Clock (in KHz) 16 O/P LEDs Jumpers 24 configurable switches 4.c System Connection Diagram (CPLDs) ni logic Pvt. Ltd., Pune 14 4d MATrix board component legend diagram Prog. Port RS-232 Port Configurable I/Os Configuration Mode Selection Regulators Rolling Display Relay Header 7 segment Displays ni logic Pvt. Ltd., Pune 15 Chapter 5: Precautions Verify the power on LED status after applying power to the trainer. Connect the 9 pin D connector of the cable to the trainer only after confirming the above During downloading make sure that the jumper selections are proper. Select the proper configuration mode during programming, else programming can fail. Take care for adaptor position before plugging on the board; this may cause damage to PLD device on power ON if plugged incorrectly. Insert the PLD adaptor by looking at the circle marks given on the baseboard and adaptor card. Do not touch the FPGA, as your body static charge may damage FPGA. Before implementation, it is necessary to lock the pins in user constraint file (UCF) as per the design and I/Os used. For downloading the bit stream, the downloading circuit requires a stable supply; hence it is recommended to use power supply given along with the trainer board. PLD devices are sensitive to surge currents and voltages. The devices supported on MATrix works 5V logic family, user can read device datasheets before applying external signals to device. Kindly remove the cables from holding its headers only. Removing the cables from holding its wires may cause damage to cable joints. ni logic Pvt. Ltd., Pune 16 Chapter 6: Design Flow Design Entry Simulation HDL (Verilog, VHDL) Hardware Description Language. Very High speed Integrated circuit HDL. Verilog having C based constructs. Functional Verification Functional simulation of the design. No timings are considered. Synthesis Process for converting design specifications into gate level netlist. Needs synthesis library containing target technology information. Implementation Combined name for processes like for translation, floorplanning, mapping, place & route, bit file generation. For locking input and output signal to the particular pins of the device user must write UCF (User Constraint File) before implementation. Output of implementation is.bit for FPGA and.jed file for CPLD, which can be directly program into the target device. Programming This is the process by which user can physically download the design programming files from PC to target device using programming cable. To program CPLD, select Boundary scan (JTAG) mode. To program FPGA, select Boundary scan, slave serial mode or Master serial Mode. ni logic Pvt. Ltd., Pune 17 Microcontroller Design Flow Source Code Entry High-level language program description. Using assembly or C language. Compile Converters the object code to low-level language. Build Builds the programming hex file. Debug Step-by-step execution of program. Program Program the controller, using ISP/external programmer. ni logic Pvt. Ltd., Pune 18 Using EDA Tools In this chapter we will see how a project can be created in Xilinx and Altera EDA tools, and how we can proceed to use MATrix to perform our experiments. We take the example of half adder and implement on both vendor devices. Design flow for Xilinx ISE series softwares Step 1: Open ISE webpack software. Step 2: Create new project Step 3: Go to project menu and select new source ni logic Pvt. Ltd., Pune 19 Step 4: Select VHDL source file, name it adder, click next, and enter entity I/Os as A, B, Sum & Carry. Step 5: Write VHDL code for half adder. ni logic Pvt. Ltd., Pune 20 Step 6: Create new source file for implementation constraint file. Name it adder_ucf, and associate with the corresponding design file. Step 7: To assign the pin location of the design, open the UCF file, to run the constraint editor where we have to lock the I/Os of design to a particular pin number. ni logic Pvt. Ltd., Pune 21 Step 8: Once the constraint editor is open, goto ports tab, and assign the pins by referring the Pin assignment chapter. Eg: net A loc =p82; Step 9: Save the UCF file and come back to project navigator. Now selecting the adder design file, run the synthesis process, there after Implementation and finally run generate programming file option. ni logic Pvt. Ltd., Pune 22 Step 10: After the all the three processes are successfully over, run the configure device (impact) option to open the impact programmer. After opening impact add Xilinx device design file, for CPLD it is *.jed file, and for FPGA it is *.bit file. Step 11: Go to operations option and select program option. ni logic Pvt. Ltd., Pune 23 Step 12: Keep the erase option enabled and click OK. Step 13: After erasing the CPLD, the programming would start and will configure the particular device. Now check the functionality on the board and verify it by applying different inputs to FPGA from switches on board. ni logic
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