65540 / 545. High Performance Flat Panel / CRT VGA Controllers. Data Sheet Revision 1.2. October

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65540 / 545 High Performance Flat Panel / CRT VGA Controllers Data Sheet Revision 1.2 October 1995 Copyright Notice Copyright 1995, Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted
65540 / 545 High Performance Flat Panel / CRT VGA Controllers Data Sheet Revision 1.2 October 1995 Copyright Notice Copyright 1995, Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without the express written permission of Chips and Technologies, Inc. Restricted Rights Legend Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at Trademark Acknowledgement CHIPS Logotype, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK, PRINTGINE, SCAT, SuperMathDX, SuperState, and WINGINE are registered trademarks of Chips and Technologies, Incorporated. CHIPSet, Super Math, WinPC, and XRAM Video Cache are trademarks of Chips and Technologies, Incorporated. IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM Monochrome Display are trademarks of International Business Machines Corporation. Hercules is a trademark of Hercules Computer Technology. MS-DOS and Windows are trademarks of Microsoft Corporation. MultiSync is a trademark of Nippon Electric Company (NEC). Brooktree and RAMDAC are trademarks of Brooktree Corporation. Inmos is a trademark of Inmos Corporation. TRI-STATE is a registered trademark of National Semiconductor Corporation. VESA is a registered trademark of Video Electronics Standards Association. VL-Bus is a trademark of Video Electronics Standards Association. All other trademarks are the property of their respective holders. Disclaimer This document is provided for the general information of the customer. Chips and Technologies, Inc., reserves the right to modify the information contained herein as necessary and the customer should ensure that it has the most recent revision of the data sheet. CHIPS makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. The customer should be on notice that the field of personal computers is the subject of many patents held by different parties. Customers should ensure that they take appropriate action so that their use of the products does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights. 65540 / 545 High Performance Flat Panel / CRT VGA Controller n n n Highly integrated design (flat panel / CRT VGA controller, RAMDAC, clock synthesizer) Multiple Bus Architecture Integrated Interface Local Bus (32-bit CPU Direct and VL) EISA/ISA (PC/AT) 16-bit Bus PCI Bus (65545) Flexible display memory configurations One 256Kx16 DRAM (512KB) Four 256Kx4 DRAMs (512KB) Two 256Kx16 DRAMs (1MB) n Advanced frame buffer architecture uses available display memory, maximizing integration and minimizing chip count n Integrated programmable linear address feature accelerates GUI performance n Hardware windows acceleration (65545) 32-bit graphics engine - System-to-screen and screen-to-screen BitBLT - 3 operand ROP's - Color expansion - Optimized for Windows BitBLT format Hardware line drawing 64x64x2 hardware cursor n Hardware pop-up icon (65545) 64x64 pixels by 4 colors 128x128 pixels by 2 colors n n High performance resulting from zero wait-state writes (write buffer) and minimum wait-state reads (internal asynchronous FIFO design) Mixed 3.3V ±0.3V / 5.0V ±10% Operation n Interface to CHIPS' PC Video to display live video on flat panel displays n Supports panel resolutions up to 1280 x 1024 resolution including 800x600 and 1024x768 n n n n n n n n n n Supports non-interlaced CRT monitors with resolutions up to 1024 x 768 / 256 colors True-color and Hi-color display capability with flat panels and CRT monitors up to 640x480 resolution Direct interface to Color and Monochrome Dual Drive (DD) and Single Drive (SS) panels (supports 8, 9, 12, 15, 16, 18 and 24-bit data interfaces) Advanced power management features minimize power consumption during: Normal operation Standby (Sleep) modes Panel-Off Power-Saving Mode Flexible on-board Activity Timer facilitates ordered shut-down of the display system Power Sequencing control outputs regulate application of Bias voltage, +5V to the panel and +12 V to the inverter for backlight operation SMARTMAP intelligent color to gray scale conversion enhances text legibility Text enhancement feature improves white text contrast on flat panel displays Fully Compatible with IBM VGA EIAJ-standard 208-pin plastic flat pack BIOS ROM 32-bit 386/486 CPU Direct or VL Local Bus, PCI Bus, or 16-bit ISA System Bus MHz Address Data Control or KByte or 1MByte Video Memory RGB H/V Sync Panel Control Panel Data 16/24 Optional PCVideo Multi-Media Interface 24 To CRT Display To Flat Panel Display System Diagram Revision / 545 Revision History Revision History Revision Date By Comment 1.1 9/94 DH Added note: Refer to Electrical Specs for maximum clock frequencies in 'Supported Video Modes' table Added note: Not all above resolutions can be supported at 3.3V and/or 5V Changed Mode 50 in Supported Video Modes-Extended Resolution Table from 16 to 16M Reset column in Reset/Setup/Test/Standby/Panel-Off Mode table was incorrect. Now reads: RESET#/Low/ / /High/High Changed note for Pin List-Bus Interface: from Drive=5V low drive and 3V high drive to IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Changed pin description: pin 25 LDEV# pin type Out/OC to Out Changed Config Reg XR01 bits 2-1 VL-Bus description for pin 23=CRESET should read pin 23=RDYRTN# Changed Ext Reg XR2D and XR2E to (CMPR Enabled) and (CMPR Disabled) and added note: For DD panels without frame acceleration, the programmed value should be doubled Updated tables for No FRC and 2-Frame FRC Updated Flat Panel Timing CD: 010 should read CD: 001 Updated Programming: FLM delay programmed in XR2C should be equal to: CRT blank time FLM front porch FLM width XR2D LP Delay (CMPR enabled) & XR2E LP Delay (CMPR disabled) Added note: Can use external MHz oscillator into XTALI (203) with XTALO (204) as no connect Updated Elec Specs: changed Max under Normal Operating Conditions from 90 to 100; memory clock is assumed to be 68 MHz not 65 MHz; and VL-Bus timing is compatible with VL-Bus Specification 2.0 Added timing for VL-Bus LDEV#, MHz, DRAM R/M/W and PC-Video and modified timing for PCI Bus Frame Clarified function of ACTI output /95 BB/MP Updated Supported Video Modes table Updated I/O Map section Added to CHIPS VGA Product Family in Register Summary Updated Extension Registers table Updated XR33, XR6C, XR6F in the Extension Registers section Added Rset formula to CRT Panel Interface Circuit Updated Interface-Optrex DMF-50351NC-FW (640x480 Color STN-DD) LCD Panel Interface example Updated 65540/545 DC Characteristics in timing section Updated Local Bus Input Setup & Hold, Local Bus Output Valid, Local Bus Output Float Delay, VL-Bus LDEV#, CRT Output, Panel Output Timing diagrams Added 65545B2 specifications Revision / 545 Table of Contents Table of Contents Section Page Introduction / Overview... 7 Minimum Chip Count / Board Space... 8 Display Memory Interface... 8 CPU Bus Interface High Performance Features Acceleration Hardware Cursor PC Video / Overlay Support Display Interface Flat Panel Displays Panel Power Sequencing CRT Displays Simultaneous Flat Panel / CRT Display.. 14 Display Enhancement Features True-Gray Gray Scale Algorithm RGB Color to Gray Scale Reduction SmartMap Text Enhancement Vertical and Horizontal Compensation Advanced Power Management Normal Operating Mode Mixed 3.3V and 5V Operation Panel Off Mode Standby Mode CRT Power Management (DPMS) CPU Activity Indicator / Timer Full Compatibility Write Protection Extension Registers Panel Interface Registers Alternate Panel Timing Registers Context Switching Reset, Setup, and Test Modes Reset Mode Setup Mode Tri-State Mode ICT (In-Circuit-Test) Mode Chip Architecture Sequencer CRT Controller Graphics Controller Attribute Controller VGA / Color Palette DAC Clock Synthesizers Configuration Inputs Virtual Switch Register Light Pen Registers BIOS ROM Interface Package Application Schematics Section Page Pinouts (65540) Pinouts (65545) Pin Diagram (65540) Pin Diagram (65545) Pin Lists Pin Descriptions - ISA/VL-Bus Interface Pin Descriptions - PCI Bus Interface (65545 only) Pin Descriptions - Display Memory Pin Descriptions - Flat Panel Interface Pin Descriptions - CRT and Clock Interface 40 Pin Descriptions - Power / Gnd / Standby Register and Port Address Summaries I/O Map CGA, MDA, and Hercules Registers EGA Registers VGA Registers VGA Indexed Registers Extension Registers Bit Registers (65545) PCI Configuration Registers (65545) Register Descriptions Global Control (Setup) Registers PCI Configuration Registers General Control & Status Registers CGA / Hercules Registers Sequencer Registers CRT Controller Registers Graphics Controller Registers Attribute Controller and VGA Color Palette Registers Extension Registers Bit Registers (65545 only) Revision / 545 Table of Contents Table of Contents Section Page Functional Description System Interface Functional Blocks Bus Interface ISA Interface VL-Bus Interface Direct Processor Interface PCI Interface Display Memory Interface Memory Architecture Memory Chip Requirements Clock Synthesizer MCLK Operation VCLK Operation Programming the Clock Synthesizer. 168 Programming Constraints Programming Example PCB Layout Considerations VGA Color Palette DAC BitBLT Engine (65545 only) Bit Block Transfer Sample Screen-to-Screen Transfer Compressed Screen-to-Screen Transfer. 173 System-to-Screen BitBLTs Hardware Cursor (65545 only) Programming Cursor Data Array Format & Layout 177 Display Mem Base Addr Formation. 178 VGA Controller Programming Copying Cursor Data to Disp Mem Setting Position, Type, & Base Addr 178 Flat Panel Timing Overview Panel Size Panel Type TFT Panel Data Width Display Quality Settings Frame Rate Control (FRC) Dither M Signal Timing Gray / Color Levels Pixels Per Shift Clock Color STN Pixel Packing Output Signal Timing LP Signal Timing FLM Output Signal Timing Blank#/DE Output Signal Timing Shift Clock Output Signal Timing Pixel Timing Sequence Diagrams Section Page Programming and Parameters General Programming Hints Parameters for Initial Boot Parameters for Emulation Modes Parameters for Monochrome LCD Panels (Panel Mode Only) Parameters for Monochrome LCD Panels (Simultaneous Mode Display) Parameters for Color TFT Panels (Panel Mode Only) Parameters for Color TFT Panels (Simultaneous Mode Display) Parameters for Color STN SS Panels (Panel & Simultaneous Mode Display) Parameters for Color STN SS Panels (Extended 4-bit Pack) Parameters for Color STN DD Panels (Panel & Simultaneous Mode Display) Parameters for Plasma Panels Parameters for EL Panels Application Schematics System Bus Interface VL-Bus / 486 CPU Local Bus Interface PCI Local Bus Interface Display Memory / PC Video Interface CRT / Panel Interface Panel Interface Examples Electrical Specifications Absolute Maximum Conditions Normal Operating Conditions DAC Characteristics DC Characteristics DC Drive Characteristics AC Test Conditions AC Characteristics Reference Clock Timing Clock Generator Timing Reset Timing Bus Timing DRAM Timing CRT Output Timing PC Video Timing Panel Output Timing Mechanical Specifications Plastic 208-PFP Package Dimensions Revision / 545 List of Tables List of Tables Table Page Table Page Feature Differences... Display Capabilities Supported Video Modes - VGA Supported Video Modes - Extended Supported Video Modes - High Refresh Vcc Pin to Interface Pin Correspondence... Reset/Setup/Test/Standby/Panel-Off Modes Configuration Pin Summary Pin List Pin Descriptions Standby Mode Panel Output Signal Status Standby Mode Memory Output Signal Status. 41 Standby Mode Bus Output Signal Status I/O Map Register Summary - CGA/MDA/Herc Modes 44 Register Summary - EGA Mode Register Summary - VGA Mode Register Summary - Indexed Registers Register Summary - Extension Registers Register Summary - 32-Bit Registers (65545) 49 Register Summary - PCI Confg Regs (65545) 50 Register List - Setup Registers... Register List - PCI Configuration Register List - General Control & Status... Register List - CGA / Hercules Registers Register List - Sequencer Register List - CRT Controller Register List - Graphics Controller Register List - Attribute Controller and VGA Color Palette Register List - Extension Registers... Register List - 32-Bit Registers (65545) DRAM Speed vs. Memory Clock Frequency. 166 Parameters - Initial Boot... Parameters - Emulation Modes Parameters - Monochrome LCD-DD Panel Mode Only Simultaneous Mode Display Parameters - Color TFT LCD Panel Mode Only Simultaneous Mode Display Parameters - Color STN-SS LCD Panel & Simultaneous Mode Display Parameters - Color STN-DD LCD 8-bit Interface Extended 4-bit Pack bit Interface (with FA) Parameters - Monochrome Plasma Parameters - Monochrome EL Panel Interface Examples Summary DK Board Connector Summary Absolute Maximum Conditions Normal Operating Conditions DAC Characteristics DC Characteristics DC Drive Characteristics AC Test Conditions AC Timing Characteristics Reference Clock Clock Generator Reset Local Bus Clock Local Bus Input Setup & Hold Local Bus Output Valid Local Bus Float Delay VL-Bus LDEV#... PCI Bus Frame PCI Bus Stop... ISA Bus DRAM Read / Write DRAM Read / Modify / Write DRAM CBR-Refresh... DRAM Self-Refresh CRT Output PC Video Panel Output Revision / 545 List of Figures List of Figures Figure Page System Diagram... 1 Panel Power Sequencing... Color Palette / DAC Block Diagram Clock Synthesizer Register Structure Pinouts (65540) Pinouts (65545) Pin List... Pin Descriptions Functional Description Clock Synthesizer Register Structure Clock Synthesizer PLL Block Diagram Clock Filter Circuit Clock Power / Ground Layout Example VGA Color Palette DAC Data Flow Possible BitBLT Orientations With Overlap 171 Screen-to-Screen BitBLT BitBLT Data Transfer Differential Pitch BitBLT Data Transfer Flat Panel Timing Monochrome 16 Gray-Level EL Monochrome LCD DD 8-bit Interface Monochrome LCD DD 16-bit Interface Color LCD TFT 9/12/16-bit Interface Color LCD TFT 18/24-bit Interface Color LCD STN 8-bit Interface Color LCD STN 16-bit Interface Color LCD STN-DD 8-bit Interface (with Frame Acceleration) Color LCD STN-DD 8-bit Interface (without Frame Acceleration) Color LCD STN-DD 16-bit Interface (with Frame Acceleration) Color LCD STN-DD 16-bit Interface (without Frame Acceleration) Application Schematics ISA Bus Interface VL-Bus / 486 Processor Direct Interface PCI Bus Interface Display Memory Interface CRT / Panel Interface Figure Page Flat Panel Interface Schematics Plasma-16 - Matsushita S EL-16 - Sharp LJ64ZU Mono DD - Epson EG9005F-LS Mono DD - Citizen G6481L-FF Mono DD - Sharp LM64P80... Mono DD - Sanyo LCM NTK Mono DD - Hitachi LMG5364XUFC... Mono DD - Sanyo LCM NAK Mono DD - Epson ECM-A Color TFT - Hitachi TM26D50VC2AA... Color TFT - Sharp LQ9D Color TFT - Toshiba LTM-09C Color TFT - Sharp LQ10D Color TFT - Sharp LQ10DX Color STN SS - Sanyo LM-CK53-22NEZ Color STN SS - Sanyo LCM NAK. 232 Color STN SS - Sharp LM64C Color STN DD - Kyocera KCL Color STN DD - Hitachi LMG9720XUFC. 235 Color STN DD - Sharp LM64C08P Color STN DD - Sanyo LCM NTK 237 Color STN DD - Hitachi LMG9721XUFC. 238 Color STN DD - Tosh. TLX-8062S-C3X Color STN DD - Opt DMF-50351NC-FW Electrical Specifications Reference Clock Timing Clock Generator Timing Reset Timing... Local Bus Clock Timing Local Bus '2x' Clock Synch Timing... Local Bus Input Setup & Hold Timing Local Bus Output Valid Timing Local Output Float Delay Timing... VL-Bus LDEV# Timing PCI Bus Frame Timing PCI Bus Stop Timing ISA Bus Timing DRAM Page Mode Read Cycle Timing DRAM Page Mode Write Cycle Timing DRAM Read/Modify/Write Cycle Timing DRAM CAS-Before-RAS (CBR) Timing DRAM 'Self-Refresh' Cycle Timing CRT Output Signal Timing PC Video Timing Panel Output Signal Timing Mechanical Specifications Plastic 208-PFP Package Dimensions Revision / 545 Introduction / Overview Introduction / Overview The / 545 High Performance Flat Panel / CRT Controllers initiate a family of 208-pin, high performance solutions for full-featured notebook / sub-notebook and other portable applications that require the highest graphics performance available. The is pin-to-pin compatible with the and adds a sophisticated graphics hardware engine for Bit Block Transfer (BitBLT), line drawing, hardware cursor, and other functions intensively used in Graphical User Interfaces (GUIs) such as Microsoft Windows. The and also use the same video BIOS, offering the system manufacturer a wide range of price / performance points while minimizing overhead for system integration and improving time-to-market. The following table indicates feature differences between the and 65545: Features Support for all flat panels 3 3 VESA Local Bus / 16-bit ISA Bus bit PCI Bus 3 Linear Addressing 3 3 Hardware Accelerator 3 Hardware Cursor 3 Pin Compatible 3 3 BIOS Compatible 3 3 The / 545 family achieves superior performance through direct connection to system processor buses up to 32-bits in width. When combined with CHIPS' advanced linear acceleration software driver technology, these devices exhibit exceptional performance compared with devices of similar architecture. The / 545 architecture provides a fast throughput to video memory, maximizing the capability of today's powerful microprocessors to manipulate graphics operations. Based on the architecture of the 65540, the adds a powerful 32-bit graphics engine to offload graphics processing from the microprocessor for maximum performance. Minimum chip-count, low-power graphics subsystem implementations are enabled through the high integration level of the / 545 family. These devices integrate the VGA-compatible graphics controller, true color RAMDAC, and dual PLL clock synthesizers. The entire graphics subsystem can be implemented with a single 256Kx16 DRAM. The 32-bit local bus interface of the / 545 family eliminates external buffers. For maximum performance, the / 545 supports an additional 256Kx16 DRAM, which provides a 32-bit video memory bus and additional display memory to support resolutions up to 1024x768 with 256 colors, 800x600 with 256 colors, and 640x480 with 16M colors. In addition, the / 545 family can support PC Video multimedia features while interfacing to a 32-bit local bus and one MByte of video memory. The / 545 family supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD) passive STN and active matrix TFT / MIM LCD, EL, and plasma panels. The / 545 family supports panel resolutions of 800x600, 1024x768, and 1280x1024. For monochrome panels, up to 64 gray scales are supported. Up to 226,981 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active matrix LCDs using the / 545 controllers. The / 545 family offers a variety of programmable features to optimize display quality. For text modes which do not fill all 480 lines of a standard VGA panel, the / 545 provides tall font stretching in the hardware. Fast vertical centering and programmable vertical stretching in graphics modes offer more options for handling modes with less than 480 lines. Three selectable color-to-grayscale reduction techniques and SMARTMAP are available for improving the viewability of color applications on monochrome panels. CHIPS' polynomial FRC algorithm reduc
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