HY11P Series Family User s Guide Mixed Signal Microcontroller

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HY11P Series Family User s Guide Mixed Signal Microcontroller Table of Contents 1 READING GUIDANCE 5 11 TERMS AND DEFINITION 6 2 CPU 8 21 CPU CORE 8 22 MEMORY 9 3 OSCILLATOR, CLOCK SOURCES AND POWER MANAGED
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HY11P Series Family User s Guide Mixed Signal Microcontroller Table of Contents 1 READING GUIDANCE 5 11 TERMS AND DEFINITION 6 2 CPU 8 21 CPU CORE 8 22 MEMORY 9 3 OSCILLATOR, CLOCK SOURCES AND POWER MANAGED MODES OSCILLATOR CPU AND PERIPHERAL CIRCUIT CLOCK SOURCES REGISTER DESCRIPTION-OPERATING CLOCK SOURCE CONTROLLER POWER MANAGED AND OPERATION MODE 32 4 RESET RESET EVENTS DESCRIPTION STATUS REGISTERS REGISTER LIST-DATA MEMORY RESET STATUS 41 5 INTERRUPT REGISTER DESCRIPTION-INTERRUPT 44 6 HARDWARE MULTIPLIER 50 7 INPUT/OUTPUT PORT, I/O PORT RELATED REGISTER INTRODUCTION BUZZER I/O PORT INPUT/OUTPUT PORT 2, I/O PORT INPUT/OUTPUT PORT 3, I/O PORT INPUT/OUTPUT PORT 4, I/O PORT INPUT/OUTPUT PORT 5, I/O PORT LOW VOLTAGE DETECT LOW VOLTAGE DETECT MANUAL REGISTER DESCRIPTION-LVD 69 9 WATCH DOG TIMER WDT MANUAL REGISTER DESCRIPTION-WDT 72 Page 2 10 TIMER-A TMA MANUAL REGISTER DESCRIPTION-TMA TIMER-B TIMER-B MANUAL REGISTER DESCRIPTION-TMB TIMER-C TIMER-C MANUAL REGISTER DESCRIPTION-TMC CAPTURE/COMPARE MODE CAPTURE MODE MANUAL COMPARE MODE MANUAL REGISTER DESCRIPTION-CAPTURE/COMPARE FREQUENCY GENERATOR, PWM/PFD PFD MODE MANUAL PWM MODE MANUAL REGISTER DESCRIPTION-PFD/PWM POWER SYSTEM VDDA MANUAL ACM MANUAL REGISTER DESCRIPTION-PWR ENHANCED COMPARATOR ECPA MANUAL LOW NOISE OPAMP LNOP MANUAL REGISTER DESCRIPTION-LNOP ANALOG-TO-DIGITAL CONVERTER SD18,Σ ADC SD18 MANUAL ANALOG CHANNEL INPUT CHARACTERISTICS ABSOLUTE TEMPERATURE SENSOR, TPS REGISTER DESCRIPTION-SD LCD 136 Page 3 191 LCD MANUAL LCD OUTPUT WAVEFORM REGISTER DESCRIPTION-LCD SERIAL PERIPHERAL INTERFACE SPI MANUAL SPI MASTER MODE SPI SLAVE MODE SPI MASTER MODULE TRANSMISSION WAY REGISTER DESCRIPTION-SPI ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER EUART MANUAL BAUD RATE GENERATOR, BRG HARDWARE PARITY CHECK EUART ASYNCHRONOUS MODE BUILT-IN EPROM BIE MANUAL REGISTER DESCRIPTION-BIE REVISION RECORD 184 Page 4 1 Reading Guidance Attention 1 HYCON Technology Corp reserves the right to change the content of this datasheet without further notice For most up-to-date information, please constantly visit our website: 2 HYCON Technology Corp is not responsible for problems caused by figures or application circuits narrated herein whose related industrial properties belong to third parties 3 Specifications of any HYCON Technology Corp products detailed or contained herein stipulate the performance, characteristics, and functions of the specified products in the independent state We does not guarantee of the performance, characteristics, and functions of the specified products as placed in the customer s products or equipment Constant and sufficient verification and evaluation is highly advised 4 Please note the operating conditions of input voltage, output voltage and load current and ensure the IC internal power consumption does not exceed that of package tolerance HYCON Technology Corp assumes no responsibility for equipment failures that resulted from using products at values that exceed, even momentarily, rated values listed in products specifications of HYCON products specified herein 5 Notwithstanding this product has built-in ESD protection circuit, please do not exert excessive static electricity to protection circuit 6 Products specified or contained herein cannot be employed in applications which require extremely high levels of reliability, such as device or equipment affecting the human body, health/medical equipments, security systems, or any apparatus installed in aircrafts and other vehicles 7 Despite the fact that HYCON Technology Corp endeavors to enhance product quality as well as reliability in every possible way, failure or malfunction of semiconductor products may happen Hence, users are strongly recommended to comply with safety design including redundancy and fire-precaution equipments to prevent any accidents and fires that may follow 8 Use of the information described herein for other purposes and/or reproduction or copying without the permission of HYCON Technology Corp is strictly prohibited Page 5 11 Terms and Definition 111 Glossary 1MW 1MegaWord 1KB 1KiloByte ADC Analog to Digital Converter Bit Bit BOR Brown-Out Reset BSR Bank Select Register Byte Byte CCP Capture and Compare CPU Central Processing Unit DAC Digital-to-Analog Converter DM Data Memory ECAP Enhance Comparator FSR File Select Register GPR General Purpose Register HAO High Accuracy Oscillator LNOP Low Noise OP AMP LPO Low Power Oscillator LSB Least Significant Bit MEM Memory MPM Main Program Memory MSB Most Significant Bit OTP One Time Program-EPROM PC Program Counter PPF PWM and PFD SD18 Sigma-Delta ADC SR Special Register SRAM Static Random Access Memory STK Stack WDT Watch Dog Timer WREG Work Register Page 6 112 Register Related Glossary [ ] Register length Register value ABC[7:0] ABC register had 0 to 7bit ABC ABC 111 ABC 11x ABC register had 3bit and value had 111 of binary x can be neglected, it can be set as 1 or 0 8 ABC ABC rw Read/Write r Read only r0 Read as 0 0 r1 Read as 1 1 w Write only w0 Write as 0 0 w1 Write as 1 1 h0 Cleared by Hardware 0 h1 Set by Hardware 1 u0 Cleared by User 0 u1 Set by User 1 - Not use! Users are forbidden to change u unchanged x unknown d depends on condition Page 7 2 CPU 21 CPU Core CPU Core (H08) adopts Harvard architecture concept in order to enhance execution efficiency Separate program memory and data memory incorporated in program memory address increases user convenience of program writing Furthermore, to strengthen user s design competitiveness, core processing methods are divided into two versions, H08A and H08B CPU features include Isolated design frame of program memory and data memory upgrades instruction execution speed and CPU efficiency Maximum address ability: 1MW for program memory and 4096KB for data memory At most 67 instructions including 16-bit look-up-table, 8x8 hardware multiplier and program memory block switch and stack control One instruction accomplished data movement from register A to register B without changing work register data One instruction accomplished utmost 16-bit FSR register data movement and address 1MW program memory look-up-table instruction Data memory operation includes Program Counter (PC), Status Register (Status) and Stack Register (Stack) data movement Processor core is divided into 2 versions, namely H08A and simplified H08B core Page 8 22 Memory Memory is composed by program memory (OTP) and data memory (SRAM) Memory size differs from diverse part number; hence product data sheets should be read with extra caution Program Memory Main Program Memory (MPM) Program Counter (PC) Stack (STK) Data Memory Special Register (SR) General Purpose Register (GPR) Memory Related Registers (x Means it constitutes several registers) PC[13:0] PCHSR[5:0],PCLATH[5:0],PCLATL[7:0] TOS[13:0] TOSH[5:0],TOSL[7:0] FSRx[9:0] FSRxH[9:8],FSRxL[7:0] INDFx INDF0[7:0],INDF1[7:0] POINCx PODECx PRINCx PLUSWx STKCN PSTATUS BSRCN POINC0[7:0], POINC1[7:0] PODEC0[7:0], PODEC1[7:0] PRINC0[7:0], PRINC1[7:0] PLUSW0[7:0], PLUSW1[7:0] STKFL[0],STKOV[0],STKUN[0],STKPRT[4:0] SKERR[0] BSR[3:0] Page 9 221 Program Memory Figure 2-1 Program Memory Flame 2211 Main Program Memory, MPM The frame of main program memory is as follows Interrupt Vector Reset Vector Maximum Address ability 1 starting from 0x00000h to 0xFFFFFh, the entire capacity is characters and it will vary with different part numbers Before the IC being written, data type of all bits is 1 After programming, the bit will show 1 or 0 according to the written data type Please be noticed that if the emulation software (HYIDE) compiling option has been configured the programming protection function, all data type will only be read as Program Counter, PC Program Counter (PC) includes shift register PCSR and buffer register PCLAT, as Figure 2-2 implicated 1 Program memory address ability varies from every product scheme Common capacitiy is 2KB(0x7FFh), 4KB(0xFFFh), 8KB(0x1FFFh) and 16KB (0x3FFFh, HY11S14 emulation IC capacity) Page 10 Figure 2-2 Program Counter Frame PC [13:0] 2 of the ICE equips with 14 bit data length and is composed by two registers: PCSRH [5:0] and PCLATL [7:0] PCLATL [7:0] and PCLATH [5:0] can be directly read/written but PCSRH [5:0] cannot Buffer register, PCLATH [5:0] must be applied to carry out indirect read and write To read PC[13:0], PCLATL[7:0] must be read first then to read PCLATH[5:0] in order to obtain correct data Any reverse order may result in incorrect data To write PC[13:0], PCLATH[5:0] must be written first then to write PCLATL[7:0] Any reverse order may result in incorrect data ORG 0000 JMP START ORG 0004H RETI START: ;jump to 0109h MVFF PCLATL,B1 INF PCLATH,F,ACCE MVL 2 ADDF B1,W,ACCE MVF PCLATL,F,ACCE ORG 0109H NOP Example 2-1 Read/Write PCLAT Example Program 2 Program memory address ability varies from every product scheme Common capacities are 2KB (0x3FFh), 4KB (0xFFFh), 8KB (0x1FFFh) and 16KB (0x3FFFh, HY11S14 emulation IC capacity) Page 11 2213 Stack, STK Stack, STK is mainly composed by Stack Index Control Register (STKCN), Top-of-Stack Register (TOSx), Stack Layer Register (STKn 3 ), Stack Error Flag Bit (SKERR) and Stack Error Reset Controller (SKRST[0]) As presented in Figure 2-3 Figure 2-3 Stack Frame Top-Of-Stack register, TOS[13:0] is 14 bit wide and is constituted by two registers, TOSH[5:0] and TOSL [7:0] When STKPRT[4:0]= 0 TOS[13:0]= 0 null, program executes CALL instruction or an interrupt (INT) is acknowledged, stack pointer STKPRT[4:0] will add 1 and write the PC address into current register, TOS[13:0] When program executes instruction RETx, STKPRT[4:0] will subtract 1 Before subtracting 1, TOS[13:0] data will be written to PC[13:0] After completion, STKPRT[4:0] will subtract 1 and change current TOS[13:0] value There is no special regulation of reading register, TOS[13:0] It can be read directly CALL instruction or interrupt (INT) can be utilized to wrtie PC[13:0] data to register, TOS[13:0] POP instruction can discard current TOS[13:0] data and may result in 1 decrement of STKPRT[4:0] and may load in new TOS[13:0] data STKFL[0] (Stack full), STKOV[0](Stack overflow) or STKUN[0](Stack underflow) may happen during stack operation processes Stack full is the early warning flag of stack overflow, executes POP instruction this time can discard current TOS[13:0] data and STKPRT[4:0] may subtract 1 and rewrite the newly appointed stack layer data into TOS[13:0] Users must be aware that when STKPRT[4:0]= 0 , executes POP insturction may not lead to stack underflow, STKPRT[4:0] data can still be 0 Therefore, users must determine if it is blank stack Stack overflow and stack underflow may result in unexpected result of program execution If there is a necessary, it is suggested to restart the IC In the processes 3 Stack layer register, STKn Every stack layer has the same length data register as that of top-of-stack register, TOS When stack index STKPRT being designated, the content of data register will be sent to TOS Page 12 of program development, stack reset control bit, SKRST[0] 4 can be configured as 1 through software When stack overflow or stack underflow take place, reset signal will be generated and SKERR[0] will be set as 1 to restart the IC Stack Full: Configure STKFL[0] as 1 , PC[13:0] is not influenced Stack Underflow: Configure STKUN[0] as 1 , PC[13:0] moves to 0x00000h, STKPRT points to 0 Level If SKRST[0] is set as 1 , reset signal will be aroused after stack underflow and SKERR[0] may be configured as 1 , STKUN[0] will be 0 after reset Stack Overflow: Configure STKOV[0] as 1 , PC[13:0] is not influened but STKPRT remains at the last layer and new values may be written in That is to say, the lastest written-in data may be safed after stack full If SKRST[0] is configured as 1 , reset signal may be generated after stack overflow and SKERR[0] may be set as 1 STKOV[0] will be set as 0 after reset Errot: Configure SKERR[0] as 1 , stack error occurred If SKRST[0] is configured 1 , reset signal will be generated after stack overflow and SKERR[0] will be placed 1 STKUN[0] and STKOV[0] will be configured as 0 after reset If stack overflow that resulted from ignorance of stack full situation and stack underflow that caused by continuously execute POP instruction happened, STKFL[0], STKOV[0] and STKOV[0] must be configured as 1 in the same time It is recommended to implement flag clearance action in order to prevent program misjudgement To ignore the known stack overflow status when writing program, it is suggested to use POP instruction to erase stack overflow flag, then to continue implementing program Otherwise, the Interrupt/Call instruction that generated from stack overflow may cape current TOS[13:0] data 4 SKRST[0] is the generated reset signal control bit of stack error Instead of direct read or write, it only can be set by developing software at the program development stage That is to say, whether to generate stack error reset signal must be determined at program developing stage If reset is chosen, after IC enpowered, SKRST [0] is set as 1, the opposite situation is set as 0 Page 13 2214 Register Decription-Program Memory Controller - no use, * read/write, w write, r read, r0 only read 0, r1 only read 1, w0 only write 0, w1 omly write 1 unimplemented bit, x unknown, u unchanged, d depends on condition Address File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 A-RESET i-reset 16H TOSH TOS[13] TOS[12] TOS[11] TOS[10] TOS[9] TOS[8] H TOSL Top-of-Stack Low Byte (TOS 7:0 ) H STKPTR STKFL STKUN STKOV STKPRT[4] STKPRT[3] STKPRT[2] STKPRT[1] STKPRT[0] AH PCLATH PC[13] PC[12] PC[11] PC[10] PC[9] PC[8] BH PCLATL PC Low Byte for PC 7:0 CH PSTATUS PD TO IDLEB BOR SKERR 000d 0 uduu d TOSU/TOSH/TOSL Top-OF-Stack Register TOSH TOS[13:8] TOSL TOS[7:0] STKPTR Stack Controller STKFL Stack full flag 1 Happened 0 Not happened STKUN Stack underflow flag 1 Happened 0 Not happened Table 2-1 Program Memory Control Register STKOV Stack overflow flag 1 Happened 0 Not happened STKPRT[4:0] Stack pointer register the 16 th layer the 15 th layer the 0 layer, TOS[13:0]=0x0000h PCLATU/PCLATH/PCLATL Program Counter, PC[13:0] PCLATH PC[13:8] PCLATL PC[7:0] PSTATUS Status Register SKERR Stack error generated reset flag 1 Happened 0 Not happened Page 14 222 Data Memory, DM Data Memory comprises Special Register (SR) and General Purpose Register (GPR), every 256byte is a segment Segment 0 and segment 1 in particular, include 128byte SR and 128byte GPR respectively Other segments contain 256byte GPR, as illustrated in Figure 2-4 Figure 2-4 Data Memory Frame Page 15 2221 Memory and Instruction H08 instruction set can be divided into A and B version Both are quite different in their memory application, such as address ability, hardware multiplier, look-up-table instruction, assistant function and arguments definition Only definition of instruction memory arguments is illustrated in this chapter Detail description of instruction arguments is depicted in Instruction chapter Instructions that contain address operation function of the instruction set have three arguments, namely f, d and a f is Data or Data Memory Address d is data storage place after operation d=0 is saved in WREG register, d=1 is saved in Data Memory Register a is the designated memory operation segment a=0 is operated in segment 0, a=1 is operated in designated segment of BSR[3:0] 2222 Segment Select Control Register Every 256 byte of data memory is set to be one segment (000h 0FF) To read or write address 0FFh register data, it is necessary to set correct segment control register BSR [3:0] and instruction argumnet a Description is as follows: When a = 0, no matter register BSR [3:0] appoints to which segment, data memory read/write instruction will only show in segment 0 When a = 1, read/write instruction of H08A CPU Core to data memory will be in compliance with the assigned segment of BSR[3:0]; read/write instruction of H08B CPU Core to data memory will be in segment 0 Page 16 MVF f,d,a a =access Ex BSR[3:0]=0 V1 equ 081h ; MVL 0AAh ;put 0AAh to W MVF V1,1,0 ; wirte W value to the 0x081h address of segment 0 Ex BSR[3:0]=2 Ex BSR[3:0]=1 V1 equ 081h MVL 0AAh ; Put 0AAh to W MVF V1,1,1 Write181h address V1 equ 081h MVL 0AAh ; Put 0AAh to W MVF 0x281h,1,1 ; write W value to the 0x281h address of segment 2 of Bank 1 to ;W value Example 2-2 Relation of Segment Selector Example Program And Data Memory 2223 Special Register Special register comprises CPU Core and peripheral function related registers, mainly are control function registers and data returned registers Undefined address or address bit of data register will show 0 whilst reading and writing There are several instruction collocation registers contained in special register, only two common types, working register (WREG) and indirect address register (FSR) are introduced herein Other special registers will be illustrated in depth in other chapter Page 17 22231 Working Register, WREG Working register is abbreviated as W, which acts as the most frequently used register for data movement, operation and diagnosis File Select Register, FSR and INDF File select register, FSR includes instruction register FSR0 [9:0], FSR1 [9:0] and index register, INDF0 [7:0] and INDF1 [7:0] Because of function similarity, only FSR0 is explained in this chapter FSR0[9:0] can be separated into two registers, FSR0H[1:0] and FSR0L[7:0] There is no need to set up BSR [4:0] to address different segments Through special instruction, only applying one instruction can write 16-bit data NDF0[7:0] is index register that can read FSR0[9:0] appointed address data of data memory H08A instruction set supports enhanced index register, the functions are characterized as follows POINC0[7:0] Events that ensued by read/write POINC0 [7:0] register by instruction The address value that FSR0 [9:0] pointed to will be sent back first Then pointer register, FSR0[9:0] value will add 1 and points to the next instruction PODEC0[7:0] Events that followed by read/write PODEC0 [7:0] register by instruction The address value that FSR0 [9:0] pointed to will be sent back first Then pointer register, FSR0[9:0] value will subtract 1 and points to the last address PRINC0[7:0] Events that followed by read/write PRINC0[7:0] register by instruction Pointer register FSR0[9:0] value will add 1 and points to the next address Current value of FSR0[9:0] appointed to address will be sent back PLUSW0 [7:0] Events that ensued by read/write PLUSW0 [7:0] register by instruction Add pointer register, FSR0[9:0] value together with working register, W value Send back current FSR0[9:0] appointed address value The register W value will be 128d General Purpose Register, GPR General purpose register, GPR is the free area for users to conduct data storage, operation, flag bit setup etc Page 18 2224 Register Description- Data Memory Controller - no use, * read/write, w write, r read, r0 only read 0, r1 only read 1, w0 only write 0, w1 omly write 1 unimplemented bit, x unknown, u unchanged, d depends on condition Address File Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 A-RESET i-reset R/W 00H INDF0 Contents of FSR0 to address data memory value of FSR0 not changed N/A N/A *,*,*,* *,*,*,* 01H POINC0 Contents of FSR0 to address data memory value of FSR0 post-incremented N/A N/A *,*,*,* *,*,*,* 02H PODEC0 Contents of FSR0 to address data memory value of FSR0 post-decremented N/A N/A *,*,*,* *,*,*,* 03H PRINC0 Contents of FSR0 to address data memory value of FSR0 pre-incremented N/A N/A *,*,*,* *,*,*,* 04H PLUSW0 Contents of FSR0 to address data memory value of FSR0 offset by W N/A N/A *,*,*,* *,*,*,* 05H INDF1 Contents of FSR1 to address data memory value of FSR0 not changed N/A N/A *,*,*,* *,*,*,* 06H POINC1 Contents of FSR1 to address data memory value of FSR0 post-incremented N/A N/A *,*,*,* *,*,*,* 07H PODEC1 Contents of FSR1 to address data memory value of FSR0 post-d
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