HT48R01/HT48R02/HT48R03 10-Pin MSOP I/O Type 8-Bit OTP MCU

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-Pin MSOP I/O Type 8-Bit OTP MCU Technical Document Tools Information FAQs Application Note HA3E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM HA6E Writing and Reading to the
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-Pin MSOP I/O Type 8-Bit OTP MCU Technical Document Tools Information FAQs Application Note HA3E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM HA6E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series HA8E Controlling the HT62 LCD Controller with the HT48 MCU Series HA49E Read and Write Control of the HT38 Features Operating voltage: f SYS =4MHz: 2.2V~5.5V f SYS =8MHz: 3.3V~5.5V f SYS =2MHz: 4.5V~5.5V 7 bidirectional I/O lines and input Interrupt input shared with I/O line 4 oscillator configuration options External crystal OSC External RC OSC Internal RC+I/O (PA5, PA6) Internal RC+RTC OSC (32768Hz) Internal RC oscillator 3 frequency selections: 4MHz/8MHz/2MHz 4MHz with % variation (2.2V~5.5V, 25C) 8MHz with % variation (3.3V~5.5V, 25C) 2MHz with % variation (4.5V~5.5V, 25C) Watchdog Timer Program memory ROM: Up to 4965 Data memory RAM: Up to 68 Buzzer driving pair and PFD supported Power-down and wake-up functions reduce power consumption Up to.5s instruction cycle with 8MHz system clock at V DD =5V All instructions executed within one or two machine cycles 4-bit or 5-bit table read instruction Up to 8-levels of subroutine nesting Bit manipulation instruction Low voltage reset function -pin MSOP package General The HT48R/HT48R2/HT48R3 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for I/O control. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power-down and wake-up functions, Watchdog Timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc. Selection Table Part No. VDD Program Memory Data Memory HT48R 2.2V~5.5V K4 648 HT48R2 2.2V~5.5V 2K4 968 HT48R3 2.2V~5.5V 4K5 68 I/O 7 I/O, Input 7 I/O, Input 7 I/O, Input Timer External Interrupt Buzzer Stack Package Types 8-bit 4 MSOP 8-bit2 6 MSOP 8-bit2 8 MSOP Rev.. December 2, 26 Block Diagram 2 H C H= 4 2 H C H= + K JA H 5 6 ) + I JHK? JE 4 A C EI JA H 2 7 : 2 )! 6 JA HHK F J + EH? K EJ, = J= A HO 6 + * * , 6 F HA I? = A H 7 : 2 ) HA I? = A H 7 : 2 ) : B5 ; 5 7 : 7 : 9, B5 ; 5 B5 ; I JHK? JE, A H 7 : 2 ) 2 )! 6 E E C / A A H= J H ) # ) $ 4-5 8,, JA H = ) 7 5 D EBJA H ) ) ) + 2 ) 2 HJ) 2 ) * 2 ) * 2 ) )! 6 2 ) ) # ) $ ) % 4-5 Pin Assignment 2 )! 6 2 ) ) * 2 ) * 8 5 5! # ' & % $ 2 ) 2 ) # ) $ ) % 4-5 8,, 2 )! 6 2 ) ) * 2 ) * 8 5 5! # ' & % $ 2 ) ) # ) $ ) % 4-5 8,, 6 & ) 6 & 4 6 & 4! 5 2 ) Rev.. 2 December 2, 26 Pin Pin Name I/O Configuration Options PA/BZ PA/BZ I/O PA2/TMR I/O PA3/INT I/O PA4/TMR I/O OSC/PA6 OSC2/PA5 I/O RC, Crystal, RTC or I/O Bidirectional 2-line I/O. Each pin can be setup as a wake-up input using a software register. Software instructions determine if each pin is a CMOS output or a Schmitt trigger input. Pull-high resistors can be connected using a pull-high software register. PA/PA are pin-shared with the BZ and BZ buzzer function pins. Bidirectional single line I/O. PA2 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with the Timer/event counter input. Bidirectional single line I/O. PA3 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with INT. Bidirectional single line I/O. PA4 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with the Timer/event counter input. Bidirectional 2-line I/O and oscillator pins. If configured as I/Os, software instructions determine if each pin is a CMOS output or a Schmitt trigger input. Pull-high resistors can be connected using a pull-high software register. A configuration option determines the choice of oscillator mode and I/O function. The four oscillator modes are:. Internal RC OSC: both pins configured as I/Os 2. External crystal OSC: both pins configured as OSC/OSC2 3. Internal RC + RTC OSC: both pins configured as OSC2, OSC. 4. External RC OSC+PA5: PA6 configured as OSC pin, PA5 configured as I/O Note: When the system clock is sourced from the internal RC OSC, there are 3 frequency options 2MHz, 8MHz and 4MHz. PA7/RES I PA7 or RES Active low schmitt trigger reset input or PA7 input. VDD Positive power supply VSS Negative power supply, ground * All pull-high resistors are controlled by an register option bit. Absolute Maximum Ratings Supply Voltage...V SS.3V to V SS +6.V Input Voltage...V SS.3V to V DD +.3V I OL Total...5mA Total Power Dissipation...5mW Storage Temperature...5C to25c Operating Temperature...4C to85c I OH Total...mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev.. 3 December 2, 26 D.C. Characteristics Ta=25C Symbol Parameter V DD Test Conditions Conditions Min. Typ. Max. Unit V DD I DD I DD2 I DD3 I DD4 I DD5 I DD6 I DD7 I STB I STB2 Operating Voltage Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Internal RC+RTC OSC, Normal Mode) Operating Current (Internal RC+RTC OSC, Normal Mode) Operating Current (Internal RC+RTC OSC, Normal Mode) Operating Current (Internal RC+RTC OSC, Slow Mode) Standby Current (WDT Enabled, RTC Off) Standby Current (WDT Disabled, RTC Off) f SYS =4MHz V f SYS =8MHz V f SYS =2MHz V 3V No load, fsys =4MHz 2 ma 5V ma 3V No load, fsys =8MHz 2 4 ma 5V 4 8 ma 5V No load, f SYS =2MHz 6 2 ma 3V No load, fsys =4MHz 2 ma 5V ma 3V No load, fsys =8MHz 2 4 ma 5V 4 8 ma 5V No load, f SYS =2MHz 6 2 ma 3V No load, fsys =32768Hz 2 A 5V 2 4 A 3V 5 A No load, system HALT 5V A 3V A No load, system HALT 5V 2 A I STB3 V IL V IH Standby Current (WDT Disabled, RTC On) Input Low Voltage for PA~PA6, TMR, TMR and INT Input High Voltage forpa~pa6, TMR, TMR and INT 3V 5 A No load, system HALT 5V A.3V DD V.7V DD V DD V V IL2 Input Low Voltage (PA7/RES).4V DD V V IH2 Input High Voltage (PA7/RES).9V DD V DD V V LVR Low Voltage Reset Configuration option: 4.2V V V LVR2 Low Voltage Reset 2 Configuration option: 3.5V V V LVR3 Low Voltage Reset 3 Configuration option: 2.V V I OL I OH R PH I/O Port Sink Current I/O Port Source Current Pull-high Resistance 3V VOL =.V DD 4 8 ma 5V 2 ma 3V VOH =.9V DD 2 4 ma 5V 5 ma 3V 2 6 k 5V 3 5 k Rev.. 4 December 2, 26 A.C. Characteristics Ta=25C Symbol Parameter V DD Test Conditions Conditions Min. Typ. Max. Unit f SYS f SYS2 System Clock (Crystal OSC, RC OSC) System Clock (Internal RC OSC) (%) 2.2V~5.5V 4 4 khz 3.3V~5.5V 4 8 khz 4.5V~5.5V 4 2 khz 4.5V~ 5.5V 3.3V~ 5.5V 2.2V~ 5.5V 2MHz, Ta=25C khz 8MHz, Ta=25C khz 4MHz, Ta=25C khz f SYS3 System Clock (32768 Crystal) Hz 2.2V~5.5V 4 khz f TIMER t WDTOSC Timer I/P Frequency (TMR) Watchdog Oscillator Period 3.3V~5.5V 8 khz 4.5V~5.5V 2 khz 3V s 5V s t RES External Reset Low Pulse Width s t SST System Start-up Timer Period Wake-up from HALT 24 t SYS t INT Interrupt Pulse Width s t LVR Low Voltage Width to Reset.25 2 ms V POR R POR VDD Start Voltage to Ensure Power-on Reset VDD Rise Rate to Ensure Power-on Reset mv.35 V/ms Note: t SYS =/f SYS, /f SYS2 or /f SYS3 Rev.. 5 December 2, 26 Functional Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter PC The program counter controls the sequence in which the instructions stored in program memory are executed and its contents specify the full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writable register (6H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. 5 O I JA +? 6 6 6! 6 6 6 6! 6 6 6 6! 6 O A J? D N A? K JA A J? D N A? K JA A J? D N A? K JA Execution Flow Mode Program Counter * * *9 *8 *7 *6 *5 *4 *3 *2 * * Initial Reset External Interrupt Timer/Event Counter Overflow Skip Program Counter+2 Loading PCL * * Jump, Call Branch # # #9 #8 #7 #6 #5 #4 #3 #2 # # Return from Subroutine S S S9 S8 S7 S6 S5 S4 S3 S2 S S Program Counter Note: *~*: Program Counter bits S~S: Stack register bits #~#: Instruction code bits PCL bits For HT48R, the Program Counter is bits wide, i.e. from *9~* For HT48R2, the Program Counter is bits wide, i.e. from *~* For HT48R3, the Program Counter is 2 bits wide, i.e. from *~* Rev.. 6 December 2, 26 Program Memory ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 244 bits for the HT48R, 2484 bits for the HT48R2 or 4965 bits for the HT48R3, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: Location H This area is reserved for program initialization. After chip reset, the program always begins execution at location H. Location 4H This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 4H. Location 8H This location is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 8H. Location CH (HT48R2/HT48R3 only) This location is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location CH. Table location Any location in the program memory can be used as look-up tables. The instructions TABRDC [m] (the current page) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (8H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table 6 & 4 6 & 4 6 & 4!, A L E? A EJE= E = JE 2 H C H=, A L E? A EJE= E = JE 2 H C H=, A L E? A EJE= E = JE 2 H C H= - N JA H = JA HHK F J5 K H K JE A - N JA H = JA HHK F J5 K H K JE A - N JA H = JA HHK F J5 K H K JE A & 6 E A H- L A J+ K JA H JA HHK F J5 K H K JE A & 6 E A H- L A J+ K JA H JA HHK F J5 K H K JE A & 6 E A H- L A J+ K JA H JA HHK F J5 K H K JE A..!!.. K F 6 = A # $ M I K F 6 = A # $ M I EJI JA H= C A I BH J! 2 H C H= A HO +.. % %.. 6 E A H- L A J+ K JA H JA HHK F J5 K H K JE A K F 6 = A # $ M I K F 6 = A # $ M I EJI JA H= C A I BH J % 2 H C H= A HO E A H- L A J+ K JA H JA HHK F J5 K H K JE A K F 6 = A # $ M I 2 H C H= A HO Program Memory.... K F 6 = A # $ M I # EJI JA H= C A I BH J. Instruction Table Location * * *9 *8 *7 *6 *5 *4 *3 *2 * * TABRDC [m] P P Table Location Note: *~*: Table location bits P~P8: Current program counter bits Table pointer bits For the HT48R, the table address location is bits, i.e. from *9~* For the HT48R2, the table address location is bits, i.e. from *~* For the HT48R3, the table address location is 2 bits, i.e. from *~* Rev.. 7 December 2, 26 word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (7H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR, and errors may occur. Therefore, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register STACK This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organised up to 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return RET or RETI instruction, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be los. Only the most recent 4 return addresses are stored. Data Memory RAM The data memory is divided into two functional groups: special function registers and general purpose data memory 648 for the HT48R, 968 for the HT48R2 or 68 for the HT48R3. Most are read/write, but some are read only. The unused space before 2H is reserved for future expanded usage and reading these locations will get H. The general purpose data memory, addressed from 2H to 5FH (HT48R), 2H to 7FH (HT48R2) or 2H to BFH (HT48R3), is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer register (MP;H). Indirect Addressing Register Location H/2H are indirect addressing registers that are not physically implemented. Any read/write operation of [H]/[2H] accesses data memory pointed to by MP (H)/MP (3H). Reading location H itself indirectly will return the result H. Writing indirectly results in no operation. The memory pointer registers (MP/MP) are 7-bit registers (HT48R/HT48R2) or 8 bit registers (HT48R3). The bit 7 of MP/MP (HT48R/ HT48R2) are undefined and reading will return the result. Any writing operation to MP/MP will only transfer the lower 7-bit data to MP. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 5H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ...) The ALU not only saves the results of data operations but also changes the status register. Rev.. 8 December 2, 26 ! # $ % & ' ) * +, -.! # $ % & ' ) * +, -. #. 6 & HA I I E C 4 A C EI JA H HA I I E C 4 A C EI JA H 2 ) * 2 6 * 9, ) ) 2 ) + 2 ) ) / A A H= 2 K HF I A, = J= A HO $ * O JA I 5 F A? E= 2 K HF I A, = J= A HO 7 K I HA = I! # $ % & ' ) * +, -.! # $ % & ' ) * +, -. %. 6 & HA I I E C 4 A C EI JA H HA I I E C 4 A C EI JA H 2 ) * 2 6 * 9, ) ) 2 ) + 2 ) ) / A A H= 2 K HF I A, = J= A HO ' $ * O JA I 5 F A? E= 2 K HF I A, = J= A HO 7 K I HA = I! # $ % & ' ) * +, -.! # $ % & ' ) * +, -. *. 6 & HA I I E C 4 A C EI JA H HA I I E C 4 A C EI JA H 2 ) * 2 6 * 9, ) ) 2 ) + 2 ) ) / A A H= 2 K HF I A, = J= A HO $ * O JA I 5 F A? E= 2 K HF I A, = J= A HO 7 K I HA = I RAM Mapping Status Register STATUS This 8-bit register (AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. Bit No. Label Function C AC C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. 3 OV 4 PDF 5 TO OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT i
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